Leaderboard

This is interesting, especially the SGX bit considering its bios disableable, and also removed from >= 12th gen. Perhaps I need to consider ignoring SGX. Currently working on a new version of the script that takes cache sizes into account. EDIT 14/Jun/2023 Script has been significantly updated and now needs testing again :P Changes: Now ignores SGX instruction set, due to being bios settable (and disabled by default on supported platforms apparently). Thanks @grouche for spotting that. After discussions with @drobbins and further digging around in gcc the script can now check L1/L2 cache sizes. After adding the above functionality, the methodology used to rank uarches no longer made sense (ranked by instruction set intersections, percentage was calculated later (intersections over cflags available on cpu) for display purposes only.) This has been changed. Ranking is now done by percentage using the following methodology: percentage calculated as above (intersections over cflags available on cpu). Cache sizes are queried and mismatches (i·e gcc expecting a larger cache than the cpu has) are penalised by halving the percentage for L1 mismatches, and/or deducting a quarter of the percentage value for L2 mismatches. Finally, a further 5% is deducted for every non-ignored instruction set that is present on the cpu but is disabled in the gcc profile (using -mno-) uarches with cache mismatches are reported separately after the initial ranking (which they are not included in) Tried to condense output to 1 line per uarch (excluding recommended uarch) This has entailed replacing tabs with a variable number of spaces, so may have slightly reduced readability. Script also identifies uarches where the current cpu actually has MORE cache than the profile expects, however this does NOT impact ranking or percentage calculation at all, it is purely informational. Added separator character lines to try to make the output more digestable